1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a T electrode in a field effect transistor.
2. Description of the Prior Art
With high integration of semiconductor devices, micropatterning of gate electrodes has been advanced. However, micropatterning of gate electrodes inevitably leads to an increase in gate resistance. As a measure against this, a method of forming a T gate electrode is employed. FIGS. 1A to 1E are sectional views, respectively, showing a semiconductor chip to explain the steps in manufacturing the T gate electrode of a conventional GaAs FET.
As shown in FIG. 1A, after an operating layer 2 is formed on a semi-insulating substrate 1, part of the surface of the operating layer 2 is selectively removed by wet etching or dry etching using a photoresist pattern as a mask, thereby forming a recess step 4. An insulating film 8 made from SiO.sub.2 is formed by LP-CVD on the obtained structure. An antireflection film 9 is formed on the insulating film 8. According to Japanese Unexamined Patent Publication No. 6-204130, this antireflection film 9 is formed by applying a silicon-based organic material by spin coating. Then, a first positive photoresist film 5A is applied on the antireflection film 9.
As shown in FIG. 1B, the resultant structure is exposed by an aligner (not shown) using a photomask (not shown). As an exposure beam, an i-line (.lambda.=365 nm) or a KrF excimer beam (.lambda.=248 nm) is used. In exposure, an exposure beam passing through the photomask is incident on an exposure region L in the photoresist film 5A. The antireflection film 9 below the photoresist film 5A has a low transmittance with respect to the exposure beam, and is made thick enough to prevent transmission of the incident beam to the under-layer of the antireflection film 9, or reflection thereof to an upper layer. For this reason, a pattern is stably formed without being influenced by reflection or interference of the exposure beam coming from the underlayer. Subsequently, the resultant structure is developed by an alkali developing solution to dissolve the exposure region, forming a resist pattern having a resist opening 6A in the recess step.
As shown in FIG. 1C, the surface of the antireflection film 9 to be exposed is processed by an oxygen (O.sub.2) plasma, and selectively changed into an inorganic-system film 9A to attain the same etching characteristics as those of the SiO.sub.2 film 8. Using the first photoresist film 5A as a mask, the inorganic-system film 9A and the SiO.sub.2 film 8 are selectively removed by dry etching with SF.sub.6 gas, thereby forming an opening portion 6B.
As shown in FIG. 1D, after the remaining photoresist film 5A is removed by an O.sub.2 plasma, the remaining antireflection film 9A is completely removed by dry etching using SF.sub.6 gas. A metal film 17 is sputtered on the entire surface including the opening portion 6B to fill the gate opening portion 6B. The following steps will be explained using an example disclosed in Japanese Unexamined Patent Publication No. 63-245961. The metal film 17 is made from WSi-Ti-Pt-Au. Using a second photoresist pattern 5B as a mask, an unnecessary portion of the metal film 17 is selectively removed by ion milling.
As shown in FIG. 1E, the photoresist pattern 5B is removed to form a gate electrode 17A. An Si.sub.3 N.sub.4 film 10 is formed by CVD, and then dry-etched using CF.sub.4 gas to leave it on only the side walls of the gate electrode 17A. Further, the resultant structure is wet-etched using a solution containing hydrofluoric acid to remove the SiO.sub.2 film 8. At this time, the Si.sub.3 N.sub.4 film 10 serves to protect the Ti layer in the metal film 17 from being etched.
The first problem in the conventional technique is that addition of the antireflection film between the photoresist film and the SiO.sub.2 film serving as a target etching film results in an increase in number of steps by the steps of forming, etching, and completely removing the antireflection film, compared to a case of forming no antireflection film.
The step of etching the antireflection film can be performed under the same conditions as those of the step of etching the SiO.sub.2 film. However, since the total film thickness which should be etched is larger than that in the case of etching only the SiO.sub.2 film, the dimensional accuracy for transferring a resist pattern to the SiO.sub.2 film decreases.
The second problem in the conventional technique is that the step of forming and processing the Si.sub.3 N.sub.4 film is added because a T gate electrode formation metal must be protected by the Si.sub.3 N.sub.4 film in order to prevent etching of the metal in the step of completely removing the SiO.sub.2 film upon forming the T gate electrode.